国際会議論文

  1. H. Kumagai, Y. Shiotsu, and S. Sugahara, “MODELING AND DESIGN OF TRANSVERSE-TYPE MICRO THERMOELECTRIC GENERATOR USING SILICON NANOWIRES”, IEEE International Conference on Micro Electro Mechanical Systems (MEMS) 2021, Online, January 25-29, 2021, paper M-136.i.
  2. D. Kitagata, S. Yamamoto, and S. Sugahara, “A New Store Energy and Latency Reduction Architecture for Nonvolatile SRAM Using STT-MTJs: Proactive Useless Data Flush Architecture”, IEEE International Electron Devices Meeting (IEDM) MRAM special session 2019, San Francisco, USA, December 7-11, 2019, paper P-25.
  3. Y. Shiotsu, S. Yamamoto, H. Funakubo, M. K. Kurosawa, and S. Sugahara, “Design of New Piezoelectronic Transistors and Their Ultralow-Voltage SRAM Application”, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2019), Grenoble, France, April 1-3, 2019, paper P11.
  4. Y. Shiotsu, T. Okubo, H. Kumagai, and S. Sugahara, “Design and Performance of Silicon Nanowire Micro Thermoelectric Generators”, 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2019), Grenoble, France, April 1-3, 2019, paper P14.
  5. Y. Shiotsu, T. Seino, N. Chiwaki, and S. Sugahara, “Thin-Film π-Type Micro TEG Using Vacuum/Insulator-Hybrid Isolation with Convex-Shape Hot-Plate Module Structure for Wearable Device Applications”, Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS) 2018, Daytona Beach, USA, December 4-7, 2018, paper PT-08c.
  6. D. Kitagata, S. Yamamoto, and S. Sugahara, “Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters”, 2nd New Generation of Circuits & Systems Conference (NGCAS2018), Valletta, Malta, November 20, 2018, pp. 182-185.
  7. D. Kitagata, H. Yoshida, S. Yamamoto, and S. Sugahara, “Virtually Nonvolatile Retention SRAM cell Using Dual-Mode Inverters”, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2018), San Francisco, USA, October 15-18, 2018, paper 13.5.
  8. D. Kitagata, S. Yamamoto, and S. Sugahara, “A New Architecture of Store Energy and Latency Reduction for Nonvolatile SRAM Based on Spintronics/CMOS-Hybrid Technology”, 2018 International Conference on Solid State Device and Materials (SSDM2018), Tokyo, Japan, September 9-13, 2018, paper B-4-03, pp. 119-120.
  9. D. Kitagata, S. Yamamoto, and S. Sugahara, “Virtually Nonovolatile Retention Flip-Flop Using FinFET Technology”, 2018 IEEE Silicon Nanoelectronics Workshop (SNW 2018), Honolulu, USA, June 17-18, 2018, paper P2-17, pp. 173-174.
  10. Y. Shiotsu, S. Yamamoto, Y. Shuto, H. Funakubo, M. K. Kurosawa, and S. Sugahara, “Design and Circuit Performance of a New Piezoelectronic Transistor”, 2018 IEEE Silicon Nanoelectronics Workshop (SNW 2018), Honolulu, USA, June 17-18, 2018, paper P2-5, pp. 149-150.
  11. T. Seino, N. Chiwaki, S. Yamashita, and S. Sugahara, “DESIGN AND PERFORMANCE OF pi-TYPE THIN-FILM NANO-TEG USING VACUUM/SiO2-HYBRID INSULATION MODULE STRUCTURE”, IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2018, Kobe, Japan, March 13-16, 2018, paper P-11, pp. 292-294.
  12. D. Kitagata, S. Yamamoto, and S. Sugahara, “Hierarchical Store-Free Architecture for Nonvolatile SRAM Using STT-MTJs”, IEEE International Electron Devices Meeting (IEDM) MRAM special session 2017, San Francisco, USA, December 2-6, 2017, paper P-23.
  13. N. Chiwaki, T. Seino, and S. Sugahara, “DESIGN AND PERFORMANCE OF TRANSVERSE-TYPE THIN-FILM NANO-TEG MODULES”, Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS) 2017, Kanazawa, Japan, November 14-17, 2017, paper PW.73.
  14. T. Seino, N. Chiwaki, S. Yamashita, and S. Sugahara, “DESIGN AND PERFORMANCE OF π-TYPE THIN-FILM NANO-TEG MODULES”, Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS) 2017, Kanazawa, Japan, November 14-17, 2017, paper PT.70.
  15. S. Sugahara, Y. Shuto, S. Yamamoto, H. Funakubo, and M. K. Kurosawa, “Piezoelectronic Transistor for Low-Voltage High-Speed Integrated Electronics”, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2017), San Francisco, USA, October 16-19, 2017, paper 16.5.
  16. T. Akushichi, D. Kitagata, Y. Shuto, and S. Sugahara, “Analysis of Spin Accumulation in a Si Channel Using CoFe/MgO/Si Spin Injectors”, Electron Device Technology and Manufacturing Conference, Toyama, Japan, February 28-March 2, 2017, paper P-15, pp. 204-205.
  17. D. Kitagata, Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis of Break-Even Time for Nonvolatile SRAM with SOTB Technology”, Electron Device Technology and Manufacturing Conference, Toyama, Japan, February 28-March 2, 2017, paper 4B-5, pp.72-74.
  18. T. Kondo, N. Chiwaki, and S. Sugahara, “Design and performance of thin-film μTEG modules for wearable device applications”, Electron Device Technology and Manufacturing Conference, Toyama, Japan, February 28-March 2, 2017, paper P-14, pp. 201-203.
  19. Y. Takamura, Y. Shuto, S. Yamamoto, H. Funakubo, M. K. Kurosawa, S. Nakagawa, and S. Sugahara, “Inverse-Magnetostriction-Induced Switching Current Reduction Technique for Spin-Transfer Torque MTJs and Its Low-Power MRAM Applications”, 2016 MRS Fall Meeting & Exhibit, Boston, America, November 27-December 2, 2016, paper EM10.5.03.
  20. Y. Shuto, S. Yamamoto, and S. Sugahara, “Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology”46th European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, pp. 87-90.
  21. Y. Shuto, S. Yamamoto, and S. Sugahara, “Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology”, International Symposium on Low Power Electronics and Design, San Francisco, USA, August 8-10, 2016, pp. 338-343.
  22. T. Akushichi, D. Kitagata, Y. Takamura, Y. Shuto, and S. Sugahara, “Spin Accumulation in a Si Channel using High-Quality CoFe/MgO/Si Spin Injectors”, 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016), Honolulu, USA, June 12-13, 2016, paper P1-27.
  23. D. Kitagata, T. Akushichi, Y. Takamura, Y. Shuto, and S. Sugahara, “Robust Design of Electric-field-assisted Nonlocal Si-MOS Spin-devices”, 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016), Honolulu, USA, June 12-13, 2016, paper P2-23, pp. 200-201.
  24. Y. Shuto, S. Yamamoto, and S. Sugahara, “Nonvolatile Power-gating Architecture for SRAM using SOTB Technology”, 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016), Honolulu, USA, June 12-13, 2016, paper P2-6, pp. 166-167.
  25. Y. Takamura, Y. Shito, S. Yamamoto, H. Funakubo, M. K. Kurosawa, S. Nakagawa, and S. Sugahara, “Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM”, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2016), Vienna, Austria, January 25-27, 2016, pp. 72-75.
  26. Y. Ikuse, T. Akushichi, Y. Shuto, Y. Takamura, and S. Sugahara, “Spin injection into silicon using CoFe/TiO2/Si tunnel contacts”, The 13th Joint MMM-Intermag Conference, San Diego, CA, USA, January 11-15, 2016, paper DT-05.
  27. Yusuke Shuto, Shuu’ichirou Yamamoto, Satoshi Sugahara, “Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology”, 4th Berkeley Symposium on Energy Efficient Electronic Systems (E3S), Berkeley, CA, USA, October 1-2, 2015.
  28. Daiki Kitagata, Taiju Akushichi, Yota Takamura, Yusuke Shuto, Satoshi Sugahara, “Design and analysis of electric-field-assisted nonlocal silicon-channel spin devices”, 2015 IEEE Silicon Nanoelectronics Workshop (SNW2015), Kyoto, Japan, June 14-15, 2015, paper 5-25.
  29. Tsuyoshi Kondo, Yu Kawame, Yota Takamura, Yusuke Shuto, Satoshi Sugahara, “Fabrication of high-quality Co2FeSi0.5Al0.5/CoFe/MgO/Si spin injectors for Si-channel spin devices”, 2015 IEEE Silicon Nanoelectronics Workshop (SNW2015), Kyoto, Japan, June 14-15, 2015, paper 6-4.
  30. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, “Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology”, 18th Design, Automation and Test in Europe (DATE15), Grenoble, France, March 9-13, 2015, paper 7.7.3, pp. 866-871.
  31. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara, “Comparative study of power-gating architectures for nonvolatile SRAM cells based on spintronics technology”, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014), Ishigaki, Okinawa, Japan, November 17-20, 2014, pp. 699-702.
  32. Yu Kawame, Taiju Akushichi, Yota Takamura, Yusuke Shuto, and Satoshi Sugahara, “Fabrication and characterization of a spin injector using a high-quality B2-ordered-Co2FeSi0.5Al0.5 /MgO /Si tunnel contact”, 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper AH-09.
  33. Taiju Akushichi, Yota Takamura, Yusuke Shuto, and Satoshi Sugahara, “Spin accumulation in Si channels using CoFe/MgO/Si and CoFe/AlOx/Si tunnel contacts with high quality tunnel barriers prepared by radical-oxygen annealing”, 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper FW-11.
  34. Yota Takamura, Taiju Akushichi, Yusuke Shuto, and Satoshi Sugahara, “Analysis and design of nonlocal spin devices with bias-induced spin-transport acceleration”, 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper GS-07.
  35. Yusuke Shuto, Katsunori Takahashi, Taiju Akushichi, and Satoshi Sugahara, “Fabrication of a CoFe/TiO2/Si tunnel contact and its spin-injector application”, 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper FW-15.
  36. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara, "Near-threshold voltage operation of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture", 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S Conference 2014), Millbrae, CA, USA, October 6-10, 2014, paper 9b.4.
  37. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara, "0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture", 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014), Yokohama, Japan, September 9-11, 2014, paper 11-4, pp.305-308.
  38. Y. Shuto, S. Yamamoto, and S. Sugahara, “Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture”, 2014 IEEE Silicon Nanotechnology Workshop (SNW2014), Honolulu, HI, USA, June 8-9, 2014, paper P2-13.
  39. R. Nakane, Y. Shuto, H. Sukegawa, Z. Wen , S. Yamamoto , S. Mitani , M. Tanaka, K. Inomata, and S. Sugahara, “Fabrication and characterization of pseudo-spin-MOSFETs using a multi-project CMOS wafer”, 58th Annual Conference on Magnetism and Magnetic Materials (MMM2013), Denver, CO, USA, November 4-8, 2013, paper GT-06.
  40. Y. Takamura, A. Sadano, T. Akushichi, T. Okishio, Y. Shuto, and S. Sugahara, “Analysis of Hanle-effect signals observed in Si-channel spin accumulation devices”, 58th Annual Conference on Magnetism and Magnetic Materials (MMM2013), Denver, CO, USA, November 4-8, 2013, paper AX-05.
  41. R. Nakane Y. Shuto, H. Sukegawa, Z.C. Wen, S. Yamamoto, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahara, “Spin-transistor characteristics of pseudo-spin-MOSFETs monolithically-integrated by utilizing a multi-project-wafer CMOS chip”, 2013 International Conference on Solid State Device and Materials (SSDM2013), Fukuoka, Japan, September 24-27, paper M-6-2, pp. 1084-1085.
  42. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara, "FinFET-based pseudo-spin-transistor: Design and performance", 2013 IEEE International Semiconductor Conference Dresden-Grenoble (ISCDG), Dresden, Germany, September 26-27, 2013.
  43. R. Nakane Y. Shuto, H. Sukegawa, Z.C. Wen, S. Yamamoto, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahara, “Monolithic Integration of Pseudo-Spin-MOSFETs Using a Custom CMOS Chip Fabricated Through Multi-Project Wafer Service”, 43rd European Solid-State Device Research Conference (ESSDERC2013), Bucharest, Romania, September 16-20, 2013, paper 1272, pp. 272-275.
  44. T. Okishio, T. Akushichi, Y. Shuto, and S. Sugahara, “Spin injection into intrinsic Si using CoFe/Mg/AlOx/Si barrier-height-controlled junction”, the 12th Joint MMM-Intermag Conference, Chicago, IL, USA, January 14-18, 2013, paper AR-04.
  45. Y. Kawame, M. Sato, Y. Shuto, and S. Sugahara, “Work-function control of half-metallic full-Heusler Co2FeSi1-xAlx thin films for Si-based spin-transistor applications”, the 12th Joint MMM-Intermag Conference, Chicago, IL, USA, January 14-18, 2013, paper EI-06.
  46. Y. Shuto, S. Yamamoto, H. Sukegawa, Z.C. Wen, R. Nakane, S. Mitani, M. Tanaka, K. Inomata, and S. Sugahra, “Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices”, 2012 IEEE International Electron Devices Meeting (IEDM2012), Decsember 10-12, 2012, San Francisco, CA, USA, paper 29.6.
  47. S. Yamamoto, Y. Shuto, and S. Sugahara, "Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications", 2012 IEEE Intl. Semiconductor Conference Dresden-Grenoble (ISCDG), September 24-26 2012, Grenoble, France, pp. 17-20.
  48. Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs”, 2012 IEEE Silicon Nanotechnology Workshop (SNW2012), June 10-11, 2012, Honolulu, HI, USA, paper 4-3.
  49. Y. Shuto, S. Yamamoto, and S. Sugahara, “Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spin-transistor architecture”, 4th IEEE Int. Memory Technology Workshop (IMW2012), May 20-23, 2012, Milano, Italy, paper 16.
  50. S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile Power-Gating FPGA Based on Spin-Transistor Architecture with Spin-Transfer-Torque MTJs”, 2012 MRS spring meeting, San Francisco, CA, USA, April 9-13, 2012, paper E4-11.
  51. Y. Takamura, and S. Sugahara, “Analysis of the Hanle effect in Si MOS inversion channels at 300K”, 56th Annual Conf. on Magnetism and Magnetic Materials (MMM), Scottsdale, USA, October 30-November 3, 2011, paper HB-12, pp. 548-529.
  52. Y. Shuto, S. Yamamoto, and S. Sugahara, “Nonvolatile SRAM based on spin-transistor architecture for nonvolatile power-gating systems”, International Symposium on Advanced Hybrid Nano Devices (IS-AHND): Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan, paper P-43.
  53. S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile power-gating FPGAs based on spin-transistor architecture”, International Symposium on Advanced Hybrid Nano Devices (IS-AHND): Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan, paper P-44.
  54. Y. Takamura, and S. Sugahara, “Analysis and design of Hanle-effect spin-transistor”, International Symposium on Advanced Hybrid Nano Devices (IS-AHND) : Prospects by World’s Leading Scientists, Tokyo, Japan, October 4-5, 2011, paper P-39, pp. 125-126.
  55. Y. Takamura, K. Hayashi, Y. Shuto, and S. Sugahara, “Formation and structural analysis of half-metallic Co2FeSi/SiOxNy/Si contacts with radical-oxynitridation-SiOxNy tunnel barrier,” International Symposium on Advanced Hybrid Nano Devices (IS-AHND) : Prospects by World’s Leading Scientists, Tokyo, Japan, October 4-5, 2011, paper P-40, pp. 127-128.
  56. M. Satoh, Y. Takamura, and S. Sugahara, “Preparation and characterization of L21-ordered full-Heusler Co2FeSi1-xAlx alloy thin films formed by rapid thermal annealing”, International Symposium on Advanced Hybrid Nano Devices (IS-AHND) : Prospects by World’s Leading Scientists, Tokyo, Japan, October 4-5, 2011, paper P-41, pp. 129-130.
  57. T. Okishio, Y. Takamura, and S. Sugahara, “Low-barrier ferromagnet source/drain MOSFETs using CoFe/Mg/AlOx/Si depinning contacts,” International Symposium on Advanced Hybrid Nano Devices (IS-AHND) : Prospects by World’s Leading Scientists, Tokyo, Japan, October 4-5, 2011, paper P-42, pp. 131-132.
  58. T. Okishio, Y. Takamura, and S. Sugahara, “Fabrication of spin-MOSFETs using CoFe/Mg/AlOx/Si tunnel junctions for the source and drain”, International Conf. on Solid State Devices and Materials (SSDM), Nagoya, Japan, September 28-30, 2011, paper J-4-4, p. 31.
  59. M. Satoh, Y. Takamura, and S. Sugahara, “Characterization of L21-ordered full-Heusler Co2FeSi1-xAlx alloy thin films formed by silicidation technique employing a silicon-on-insulator substrate”, Electronic Materials Conf. (EMC) 2011, Santa Barbara, USA, June 22-24, 2011, paper DD-10, p. 96.
  60. Y. Takamura, K. Hayashi, Y. Shuto, and S. Sugahara, “Formation of half-metallic tunnel junctions of Co2FeSi/SiOxNy/Si using radical oxynitridation technique”, Electronic Materials Conf. (EMC) 2011, Santa Barbara, USA, June 22-24, 2011, paper DD-9, p. 96
  61. Y. Shuto, S. Yamamoto, and S. Sugahara, “Evaluation and control of break-even time for nonvolatile SRAM using pseudo-spin-MOSFETs with spin-transfer-torque MTJs”, IEEE International Magnetics Conference 2011 (INTERMAG), April 25-29, 2011, Taipei, Taiwan, paper FR-02.
  62. S. Yamamoto, Y. Shuto, and S. Sugahara, “Application of NV-DFF and NV-SRAM using spin-transistor Architecture with spin transfer torque MTJs to nonvolatile power-gating FPGA”, IEEE International Magnetics Conference 2011 (INTERMAG), Taipei, Taiwan, April 25 - 29, 2011, paper FR-03.
  63. S. Yamamoto, Y. Shuto, and S. Sugahara, “Power-gating ability and power aware design of nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs”, IEEE International Magnetics Conference 2011 (INTERMAG), Taipei, Taiwan, April 25 - 29, 2011, paper FR-04.
  64. Y. Shuto, Y. Takamura, and S. Sugahara, “Numerical simulation analysis of nonlocal multi-terminal devices for spin current detection in semiconductors”, 55th Annual Conference on Magnetism and Magnetic Materials (MMM2010), Atlanta, GA, USA, November 14-18, 2010, paper DD-04.
  65. Y. Takamura, T. Sakurai, R. Nakane, Y. Shuto, and S. Sugahara, “Comparative study of full-Heusler Co2FeSi and Co2FeGe alloy thin films formed by rapid thermal annealing”, 55th Annual Conference on Magnetism and Magnetic Materials (MMM2010), Atlanta, USA, November 14-18, 2010, paper CV-02.
  66. Y. Shuto, R. Nakane, W. H. Wang, H. Sukegawa, S. Yamamoto, M. Tanaka, K. Inomata, and S. Sugahara, “A new spin-functional MOSFET based on MTJ technology: Pseudo-spin-MOSFET”, The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI), Tokyo, Japan, August 1-4, 2010, paper P2-71.
  67. Y. Shuto, S. Yamamoto, and S. Sugahara, “Operating analysis of nonvolatile SRAM using pseudo-spin-MOSFETs”, The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI), Tokyo, Japan, August 1-4, 2010, paper P2-72.
  68. T. Sakurai, Y. Takamura, R. Nakane, Y. Shuto, and S. Sugahara, “Epitaxial germanidation of full-Heusler Co2FeGe alloy thin films by rapid thermal annealing”, The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI), Tokyo, Japan, August 1-4, 2010, paper P2-22.
  69. Y. Takamura, R. Nakane, and S. Sugahara, “Disordered structures in full-Heusler Co2FeSi alloy thin films formed by rapid thermal annealing”, The 6th International Conference on the Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI), Tokyo, Japan, August 1-4, 2010, paper P2-21.
  70. K. Hayashi, Y. Takamura, R. Nakane, and S. Sugahara, “Formation of Co2FeSi/SiN/Si tunnel junctions for Si-based spin transistors”, 11th Joint MMM-Intermag Conference, Washington, D. C., USA, January 18-22, 2010, paper HH-02.
  71. Y. Takamura, and S. Sugahara, “X-ray diffraction study for atomic disorder in full-Heulser alloy thin films using Co x-ray source”, 11th MMM-Intermag Conference, Washington, D. C., USA, January 18-22, 2010, paper HH-09.
  72. Shuu’ichirou Yamamoto, and Satoshi Sugahara, “Nonvolatile delay flip-flop using pseudo-spin-MOSFETs and its power-gating applications”, the 11th Joint MMM-Intermag Conference, Washington, D. C., USA, January 18-22, 2010, paper DT-03.
  73. Y. Shuto, S. Yamamoto, and S. Sugahara, “Operating analysis of nonvolatile SRAM using pseudo-spin-MOSFETs”, 11th Joint MMM-Intermag Conference, Washington, D. C., USA, January 18-22, 2010, paper DT-02.
  74. Shuu’ichirou Yamamoto, and Satoshi Sugahara, “Variability-Tolerant CMOS Gates Using Functional MOSFETs with Resistive Switching Devices”, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, Sendai, Japan, 2009, pp. 810-811.
  75. Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis and design of nonvolatile SRAM using spintronics technology”, Non-volatile Memory Technology Symposium 2009 (NVMTS09), Portland, OR, USA, October 25-28, 2009, paper P7.
  76. Y. Takamura, and S. Sugahara, “Half-metallic ferromagnet technologies for spin-functional MOSFETs”, Intl. Conf. “Silicon Nano Devices in 2030: Prospects by world’s leading scientists”, Tokyo, Japan, October 13-14, 2009, paper P-48.
  77. Y. Shuto, R. Nakane, H. Sukegawa, S. Yamamoto, M. Tanaka, K. Inomata, and S. Sugahara, “Fabrication and characterization of pseudo-spin-MOSFETs”, Intl. Conf. “Silicon Nano Devices in 2030: Prospects by world’s leading scientists”, Tokyo, Japan, Octorber 13-14, 2009, paper P-49, pp.148-149.
  78. Shuu’ichirou Yamamoto, Yusuke Shuto, and Satoshi Sugahara, “Nonvolatile power-gating microprocessor concepts using nonvolatile SRAM and flip-flop”, Intl. Conf. “Silicon Nano Devices in 2030: Prospects by world’s leading scientists”, Tokyo, Japan, Octorber 13-14, 2009, paper P-50.
  79. Shuu’ichirou Yamamoto, Yusuke Shuto, and Satoshi Sugahara, “Nonvolatile SRAM (NV-SRAM) Using Functional MOSFET Merged with Resistive Switching Devices”, Proceedings of IEEE 2009 Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, September 13-16, 2009, pp. 531-534.
  80. K. Hayashi, Y. Takamura, R. Nakane, and S. Sugahara, “Preparation and characterization of full-Heusler Co2FeSi alloy thin films on amorphous insulator films”, IEEE International Magnetics Conference (INTERMAG 09), Sacramento, CA, USA, May 4-8, 2009, paper ES-08.
  81. Shuu’ichirou Yamamoto, and Satoshi Sugahara, “Nonvolatile delay flip-flop using magnetic tunnel junctions with current-induced magnetization switching architecture”, IEEE International Magnetics Conference (INTERMAG 09), Sacramento, CA, USA, May 4-8, 2009, paper ET-01.
  82. Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis and Design of Nonvolatile SRAM Using MOSFET-Based Spin-Transistors”, IEEE International Magnetics Conference (INTERMAG 09), Sacramento, CA, USA, May 4-8, 2009, paper CT-02, p. 195.
  83. Y. Takamura, R. Nakane, and S. Sugahara, “Analysis of L21-ordering in full-Heusler Co2FeSi alloy thin films formed by rapid thermal annealing”, 53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008), Austin, TX, USA, November 10-14, 2008, paper DD-03, p. 230-231.
  84. Y. Shuto, S. Yamamoto, and S. Sugahara, “Novel nonvolatile SRAM architecture using MOSFET-based spin-transistors”, 53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008), Austin, TX, USA, November 10-14, 2008, paper CT-02, p. 195.
  85. S. Yamamoto, and S. Sugahara, “Analysis and design of nonvolatile SRAM using magnetic tunnel junctions with current-induced magnetization switching technology”, 53rd Annual Conference on Magnetism and Magnetic Materials (MMM2008), Austin, TX, USA, November 10-14, 2008, paper CT-04, p. 196.
  86. Y. Takamura, Y. Nagahama, A. Nishijima, R. Nakane, and S. Sugahara, “Formation of Si- and Ge-based Full-Heusler Alloy Thin Films Using SOI and GOI Substrates for the Half-Metallic Source and Drain of Spin Transistors”, Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME2008), Honolulu, HI, USA, October 12-17, 2008, session E15-E23, paper 2480.
  87. Y. Shuto, M. Tanaka, and S. Sugahara, “Germanium-based ferromagnetic semiconductor Ge1-xFex for silicon spintronics", Pacific Rim Meeting on Electrochemical and Solid-state Science (PRiME2008), Honolulu, HI, USA, October 12-17, 2008, session E15-E23, peper 2481.
  88. Y. Takamura, A. Nishijima, Y. Nagahama, R. Nakane, and S. Sugahara, “Fabrication Technique of Si- and Ge-based Full-Heusler Alloys for Half-metallic Source/Drain Spin MOSFETs”, The Fourth International Nanotechnology Conference on Communication and Cooperation (INC4), Tokyo, Japan, April 14-17, 2008, paper P-19.
  89. Y. Shuto, M. Tanaka, and S. Sugahara, “Epitaxial growth and characterization of Germanium-based ferromagnetic semiconductor thin films for silicon spintronics”, The Forth International Nanotechnology Conference on Communication and Cooperation (INC4), Tokyo, Japan, April 14-17, 2008, paper P-18.
  90. S. Dissanayake, S. Tanabe, S. Sugahara, M. Takenaka, and S. Takagi, “Effect of Annealing on (100) and (110) Oriented pseudo-GOI pMOSFETs Fabricated by Ge Condensation Method”, The 5th International Symposium on Control of Semiconductor Interfaces -for Next Generation ULSI Process Integrations- (ISCSI-V), Tokyo, Japan, November 12-14, 2007, paper OB3-3, pp. 233-234.
  91. S. Takagi, H. Matsubara, M. Nishikawa, T. Sasada, R. Nakane, S. Sugahara, and M. Takenaka, “Superior MOS Interface Properties of GeO2/Ge Structures Fabricated by Ozone Oxidation”, The 5th International Symposium on Control of Semiconductor Interfaces -for Next Generation ULSI Process Integrations- (ISCSI-V), Tokyo, Japan, November 12-14, 2007, paper OA2-1, pp. 65-66.
  92. Y. Takamura, R. Nakane, H. Munekata, and S. Sugahara, “Preparation of full Heusler alloys on silicon on insulator substrates employing rapid thermal annealing”, 52nd Annual Conference on Magnetism and Magnetic Materials (MMM2007), Tampa, FL, USA, November 5-9, 2007, paper BQ-05, p. 116.
  93. Y. Shuto, M. Tanaka, and S. Sugahara, “Crystallographic and magnetic properties of epitaxially grown Ge1-xFex thin films on Si(001) substrates”, 52nd Annual Conference on Magnetism and Magnetic Materials (MMM2007), Tampa, FL, USA, November 5-9, 2007, paper CG-12, p. 168.
  94. S. Yamamoto, and S. Sugahara, “Nonvolatile SRAM and flip-flop architectures using magnetic tunnel junctions with current-induced magnetization switching technology”, 52nd Annual Conference on Magnetism and Magnetic Materials (MMM2007), Tampa, FL, USA, November 5-9, 2007, paper HP-02, p. 481.
  95. S. Takagi, T. Uehara, S. Tanabe, H. Matsubara, R. Nakane, M. Takenaka, and S. Sugahara, “Effects of Atomic Hydrogen Annealing on Reduction of Leakage Current in Ultrathin Si/Ge/Si-On-Insulator Metal Source/Drain p-Channel MOSFETs”, 34th International Symposium on Compound Semiconductors (ISCS2007), Kyoto, Japan, October 15-18, 2007, p. 132.
  96. Y. Shuto, M. Tanaka, and S. Sugahara, “Magneto-Optical and Magneto-Transport Properties of Ferromagnetic Ge1-xFex Thin Films Grown on Si (001) Substrates”, 4th International School and Conference on Spintronics and Quantum Information Technology (Spintech IV), Maui, HI, USA, June 17-22, 2007, paper P-33, pp. 101-102.
  97. S. Yada, M. Tanaka, and S. Sugahara, “Structural and Magnetic Properties of Self-Organized Ge1-xMnx Nanocolumns in Epitaxially Grown Mn-Doped Ge Thin Films”, 4th International School and Conference on Spintronics and Quantum Information Technology (Spintech IV), Maui, HI, USA, June 17-22, 2007, paper P-44, pp. 114-115.
  98. S. Takagi, T. Maeda, N. Taoka, M. Nishizawa, Y. Morita, K. Ikeda, Y. Yamashita, M. Nishikawa, H. Kumagai, R. Nakane, S. Sugahara, and N. Sugiyama, “Gate Dielectric Formation and MIS Interface Characterization on Ge”, The 15th Biennial Conference on Insulatring Films on Semiconductors (INFOS2007), Athene, Greece, June 20-23, 2007, pp. 2314-2319.
  99. S. Dissanayake, H. Kumagai, T. Uehara, Y. Shuto, S. Sugahara, and S.Takagi, “(110) Ultra-thin GOI p-MOSFETs Fabricated by Ge Condensation Method”, The 5th International Conference on SiGe(C) Epitaxy and Heterostructures (ICSI-5), Marseille, France, May 20-24, 2007, paper S6-O17, pp. 57-58.
  100. S. Sugahara，“Perspective on Spin-Transistor Electronics”, The 2007 International Meeting for Future of Electron Devices Kansai, Osaka, Japan, April 23-24, 2007, paper K-3.
  101. S. Sugahara，“Perspective on Si-Based Spin-Transistor Electronics”, 3rd Intlernational Nanotechnology Conference on Communication and Cooperation (INC3), Brussels, Belgium, April 16-19, 2007.
  102. S. Yada, M. Tanaka, and S. Sugahara, “Kinetically-Controlled Epitaxial Growth of Ferromagnetic Ge1-xMnx Thin Films”, 10th Joint MMM-Intermag Conference, Baltimore, MD, USA, January 7-11, 2007, paper AU-10, p. 72.
  103. Y. Shuto, M. Tanaka, and S. Sugahara, “Epitaxial Growth and Properties of Ferromagnetic Ge1-xFex Thin Films on Si (001)”, 10th Joint MMM-Intermag Conference, Baltimore, MD, USA, January 7-11, 2007, paper FT-14, p. 406.
  104. S. Takagi, and S. Sugahara, “Comparative Study on Influence of Subband Structures on Electrical Characteristics of III-V Semiconductor, Ge and Si Channel n-MISFETs”, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), Yokohama, Japan, September 12-15, 2006, paper H-9-1, pp. 1056-1057.
  105. M. Shichijo, R. Nakane, S. Sugahara, and S. Takagi, “Fabrication of III-V-O-I(III-V on Insulator) Structures on Si Using Micro-Channel Epitaxy with a Two-Step Growth Technique”, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), Yokohama, Japan, September 12-15, 2006, paper I-8-1, pp. 1088-1089.
  106. T. Uehara, H. Matsubara, S. Sugahara, and S.Takagi, “Ultra-Thin Ge-on-Insulator(GOI) Metal S/D p-Channel MOSFETs Fabricated by Low Temperature MBE Growth”, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), Yokohama, Japan, September 12-15, 2006, paper H-8-2, pp. 1050-1051.
  107. T. Hoshii, S. Sugahara, and S. Takagi, “Effect of Tensile Strain on Gate and Substrate Currents of Strained-Si n-MOSFETs”, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), Yokohama, Japan, September 12-15, 2006, paper H-1-3, pp. 164-165.
  108. H. Kumagai, M. Shichijo, H. Ishikawa, T. Hoshii, S. Sugahara, Y. Uchida, and S. Takagi, “Fabrication of SiO2/Ge MIS Structures by Plasma Oxidation of Ultrathin Si Films Grown on Ge”, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), Yokohama, Japan, September 12-15, 2006, paper J-6-23, pp. 398-399
  109. Y. Shuto, M. Tanaka, and S. Sugahara, “Ferromagnetism in Epitaxially Grown Fe-Doped Ge Thin Films on Ge(001) Substrates”, 17th International Conference on Magnetism (ICM-2006), Kyoto, Japan, August 20-25, 2006, paper FrA2-D-3, p. 119.
  110. S. Sugahara, “Spin MOSFETs As a Basis for Silicon-Based Spin-Electronics”, 4th International Conference on Physics and Application of Spin-Related Phenomena in Semiconductors (PASPS-IV), Sendai, Japan, August 15-18, 2006, paper R-4, p. 153.
  111. S. Yada, M. Tanaka, and S. Sugahara, “Ferromagnetism in Mn-Doped Amorphous Ge Thin Films”, 4th International Conference on Physics and Application of Spin-Related Phenomena in Semiconductors (PASPS-IV), Sendai, Japan, August 15-18, 2006, paper PB-36, p. 119.
  112. Y. Shuto, M. Tanaka, and S. Sugahara, “Structural and Magnetic Properties of Ferromagnetic Semiconductor Ge1-xFex Thin Films Grown by LT-MBE”, 4th International Conference on Physics and Application of Spin-Related Phenomena in Semiconductors (PASPS-IV), Sendai, Japan, August 15-18, 2006 paper C-3, p. 82.
  113. R. Nakane, M. Tanaka, and S. Sugahara, “Preparation of Ferromagnetic Silicide Fe1-xSix Using Silicon-on-Insulator Substrates for Si-Based Spin-Electronic Devices”, 50th Annual Conference on Magnetism and Magnetic Materials (MMM2005), San Jose, CA, USA, October 30 - November 3, 2005, paper DS-01, p. 198
  114. Y. Shuto, M. Tanaka, and S. Sugahara, “Epitaxial Growth and Magnetic Properties of a New Group IV Ferromagnetic Semiconductor Ge1-xFex”, 50th Annual Conference on Magnetism and Magnetic Materials (MMM2005), San Jose, CA, USA, October 30 - November 3, 2005, paper BG-04, p. 64.
  115. S. Sugahara, “MOSFET Type of Spin Transistor As a Beyond-CMOS Device Using Spin Degrees of Freedom”, 2005 International Conference on Solid State Devices and Materials (SSDM2005), Kobe, Japan, September 13-15, 2005, Rump session: Beyond the Scaling Limit-Innovative Devices and Materials-.
  116. S. Takagi, K. Takeda, S. Sugahara, and T. Numata, “Examination of the Universality of Hole Mobility in Strained-Si p-MOSFETs”, 2005 International Conference on Solid State Devices and Materials (SSDM2005), Kobe, Japan, September 13-15, 2005, paper B-2-1, pp. 38-39.
  117. S. Sugahara, “Spin MOSFETs for Integrated Spin-Electronics”, 6th International Workshop on Future Information Processing Technologies (IWFIPT), Asheville, NC, USA, August 29 - September 1, 2005, Panel Session III: Beyond-CMOS Electronic Devices.
  118. S. Yada, K. L. Lee, M. Tanaka, and S. Sugahara, “Ferromagnetism in Epitaxially Grown Ge1-xMnx Thin Films on Ge(001) substrates”, The 3rd International School and Conference on Spintronics and Quantum Information Technology (Spintech III), Awaji Island, Japan, August 1-5, 2005, paper P-31, p. 91.
  119. R. Nakane, J. Kondo, S. Sugahara, and M. Tanaka, “Current-Induced Magnetization Switching in Epitaxial MnAs/NiAs/MnAs Heterostructures on GaAs Substrates”, The 3rd International School and Conference on Spintronics and Quantum Information Technology (Spintech III), Awaji Island, Japan, August 1-5, 2005, paper P-53, p. 113.
  120. S. Sugahara, “Spin MOSFETs As a Basis for Integrated Spin Electronics”, 5th IEEE conference on Nanotechnology (IEEE-NANO 2005), Nagoya, Japan, July 11-15, 2005, paper TU-P5-1, p. 24.
  121. R. Nakane, M. Tanaka, and S. Sugahara, “Formation and Characterization of Ferromagnetic Silicide Fe1-xSix for Si-Based Spintronic Devices”, 47th Annual TMS Electronic Materials Conference (EMC), Santa Barbara, CA, USA, June 22-24, 2005, paper J10, Late News.
  122. S. Sugahara, and M. Tanaka, “Spin MOSFETs using ferromagnetic Schottky barrier contacts for the source and drain”, 63rd Device Research Conference (DRC), Santa Barbara, CA, USA, June 20-22, 2005, paper V.C-2, pp. 211-212.
  123. S. Sugahara, and M. Tanaka, “A Spin Metal-Oxide-Semiconductor Field-Effect-Transistor (Spin MOSFET) Using a Ferromagnetic Semiconductor for the Channel Region”, 49th Annual Conference on Magnetism and Magnetic Materials (MMM2004), Jacksonville, FL, USA, November 7-11, 2004, paper CR-04, p. 147.
  124. S. Sugahara, and M. Tanaka, “Theoretical Analysis of a Spin Metal-Oxide-Semiconductor Field-Effect-Transistor (Spin MOSFET) Using Ferromagnetic Schottky Contacts for the Source and Drain”, 2004 International Conference on Molecular Beam Epitaxy (MBE2004), Edinburgh, Scotland, August 22-27, 2004, paper THP33, p. 451.
  125. S. Sugahara, K. L. Lee, and M. Tanaka, “Low-Temperature Molecular Beam Epitaxy of Heavily Mn-Doped Si Thin Films on Si(001) Substrates”, 2004 International Conference on Molecular Beam Epitaxy (MBE2004), Edinburgh, Scotland, August 22-27, 2004, paper THP34, p. 453.
  126. K. L. Lee, M. Tanaka, and S. Sugahara, “Low-Temperature Molecular-Beam-Epitaxy of Ferromagnetic Mn-Doped Ge Thin Films on Si(001) Substrates”, 2004 International Conference on Molecular Beam Epitaxy (MBE2004)”, Edinburgh, Scotland, August 22-27, 2004, paper FB1.4, p. 481.
  127. R. Nakane, J. Kondo, M. W. Yuan, S. Sugahara, and M. Tanaka, “Growth and Magnetic Properties of epitaxial metallic MnAs/NiAs/MnAs Heterostructures Grown on Exact GaAs(111)B Substrates”, 2004 International Conference on Molecular Beam Epitaxy (MBE2004), Edinburgh, Scotland, August 22-27, 2004, paper THA1.2, p. 315.
  128. S. Sugahara, K. L. Lee, and M. Tanaka, “Low-Temperature Molecular Beam Epitaxy of Mn-doped Si thin films”, The 3rd International Conference on Physics and Applications of Spin-Related Phenomena in Semiconductors (PASPS III), Santa Barbara, CA, USA, July 21-23, 2004, paper 042, p. 89.
  129. S. Sugahara, and M. Tanaka, “A Ballistic Spin MOSFET Using Ferromagnetic Schottky Contacts for the Source and Drain”, The 3rd International Conference on Physics and Applications of Spin-Related Phenomena in Semiconductors (PASPS III), Santa Barbara, CA, USA, July 21-23, 2004, paper 132, p. 140.
  130. K. L. Lee, M. Tanaka, and S. Sugahara, “Epitaxial Growth and Magnetic Properties of Mn-Doped Ge Thin Films on Si(001) Substrates”, The 3rd International Conference on Physics and Applications of Spin-Related Phenomena in Semiconductors (PASPS III), Santa Barbara, CA, USA, July 21-23, 2004, paper 055, p. 96.
  131. R. Nakane, S. Sugahara, and M. Tanaka, “Epitaxial Growth and Magnetic Properties of MnAs/III-V(GaAs, AlAs)/MnAs Heterostructures on Exact GaAs(111)B Substrates”, The 3rd International Conference on Physics and Applications of Spin-Related Phenomena in Semiconductors (PASPS III), Santa Barbara, CA, USA, July 21-23, 2004, paper 153, p. 153.
  132. S. Sugahara, K. L. Lee, T. Matsuno, and M. Tanaka, “Epitaxial Growth and Magnetic Properties of Si1-xMnx Thin Films”, 2004 MRS Spring Meeting, San Francisco, CA, USA, April 12-16, 2004, paper G2.5, p. 146.
  133. S. Sugahara, T. Matsuno, and M. Tanaka, “Nonvolatile Memory and Reconfigurable Logic Applications of Spin MOSFETs”, 2004 MRS Spring Meeting, San Francisco, CA, USA, April 12-16, 2004, paper G4.7, p. 150.
  134. S. Sugahara, K. L. Lee, and M. Tanaka, “Spin MOSFETs for Spintronic Integrated Circuits”, 2004 MRS Spring Meeting, San Francisco, CA, USA, April 12-16, 2004, paper G5.8, p. 153.
  135. S. Sugahara, and M. Tanaka, “A Spin MOSFET Using Half-Metallic Source and Drain”, 9th Joint MMM-Intermag Conference, Anaheim, CA, USA, January 5-9, 2004, paper GB-11, p. 357.
  136. R. Nakane, S. Sugahara, and M.Tanaka, “The Effect of Post-Growth Annealing on the Morphology and Magnetic Properties of MnAs Thin Films Grown on GaAs(001) Substrates”, 9th Joint MMM-Intermag Conference, Anaheim, CA, USA, January 5-9, 2004, paper AE-08, p. 28.
  137. S. Sugahara, and M. Tanaka, “A Spin MOSFET Using Half-Metallic-Ferromagnet Contacts for the Source and Drain”, International Workshop on Nano-Scale Magnetoelectronics, Nagoya, Japan, November 25-27, 2003, paper P1, p. 47.
  138. T. Matsuno, S. Sugahara, and M. Tanaka, “Design and Analysis of Reconfigurable Logic Gates Using the Spin MOSFET”, International Workshop on Nano-Scale Magnetoelectronics, Nagoya, Japan, November 25-27, 2003, paper P2, p. 48.
  139. S. Sugahara, R. Nakane, K. L. Lee, and M. Tanaka, “Magnetic Coupling and Tunneling Magnetoresistance of Fully Epitaxial MnAs/AlAs/MnAs Ferromagnetic Tunnel Junctions”, International Conference and School Semiconductor spintronics and Quantum Information Technology (Spintech II), Brugge, Belgium, August 4-6, 2003, paper 053, p. 62.
  140. S. Sugahara, and M. Tanaka, “A Ferromagnetic Schottky Source/Drain MOSFET”, International Conference and School Semiconductor spintronics and Quantum Information Technology (Spintech II), Brugge, Belgium, August 4-6, 2003, paper 089, p.76.
  141. T. Matsuno, S. Sugahara, and M. Tanaka, “Reconfigurable Logic Gates Based on Spin MOSFET”, International Conference and School Semiconductor spintronics and Quantum Information Technology (Spintech II), Brugge, Belgium, August 4-6, 2003, paper 086, p. 74.
  142. R. Nakane, S. Sugahara, and M. Tanaka, “Magnetic Properties of Fully Epitaxial Metallic MnAs/NiAs/MnAs Trilayers Grown on GaAs(001) Substrates”, International Conference and School Semiconductor spintronics and Quantum Information Technology (Spintech II), Brugge, Belgium, August 4-6, 2003, paper 042, p. 58.
  143. S. Sugahara, and M. Tanaka, “Proposal of a Novel Spin Transistor Based on Spin-Filtering in a Ferromagnetic Barrier Layer: A Spin-Filter Transistor”, The 11th International Conference on Modulated Semiconductor Structures (MSS11), Nara, Japan, July 14-18, 2003, paper PC49, p. 458-459.
  144. R. Nakane, S. Sugahara, and M.Tanaka, “Epitaxial Growth and Magnetic Properties of MnAs/NiAs/MnAs Spin-Valve Trilayers on GaAs(001) Substrates”, The 11th International Conference on Modulated Semiconductor Structures (MSS11), Nara, Japan, July 14-18, 2003, paper PB77, pp. 319-320.
  145. S. Sugahara, and M. Tanaka, “Fully Epitaxial MnAs/AlAs/MnAs Ferromagnetic Tunnel Junctions Grown on GaAs(111)B Substrates: The Influence of Crystallinity on Tunneling Magnetoresistance”, 47th Conference on Magnetism and Magnetic Materials (MMM2002), Tampa, FL, USA, November 11-15, 2002, paper AA-09, p. 11.
  146. S. Sugahara, and M. Tanaka, “Epitaxial Growth and Magnetic Properties of Single-Crystal MnAs/AlAs/ MnAs Magnetic Tunnel Junctions on Exact (111)B GaAs Substrates: The Effect of an Ultrathin GaAs Buffer Layer”, 2002 International Conference on Molecular Beam Epitaxy (MBE XII), San Francisco, CA, USA, September 15-20, 2002, paper TuB3.3, p. 119.
  147. S. Sugahara, and M. Tanaka, “Fully Epitaxial MnAs/AlAs/MnAs Ferromagnetic Tunnel Junctions Grown on Vicinal GaAs(111)B Substrates”, 46th Conference on Magnetism and Magnetic Materials (MMM2001), Seattle, WA, USA, November 12-16, 2001, paper DB-12, p. 141.
  148. S. Sugahara, and M. Tanaka, “Growth Characteristics and Magnetic Properties of MnAs/AlAs/MnAs trilayer heterostructures grown on vicinal GaAs(111)B substrates”, 10th International Conference on Modulated Semiconductor Structures (MSS10), Linz, Austria, July 23-27, 2001, paper ThP30, p. 195.
  149. S. Sugahara, F. Yamagishi, and M. Tanaka, “Ferromagnet (MnAs)/Semiconductor (GaAs, AlAs)/Ferromagnet (MnAs) trilayer heterostructures on (111)B GaAs vicinal substrates: Epitaxial Growth and Magnetic Properties”, The 13th International Conference on Crystal Growth in Conjunction with the 11th International Conference on Vapor Growth and Epitaxy (ICCG-13/ICVGE-11), Kyoto, Japan, July 30 - August 4, 2001, paper 31a-S11-05, p. 18.
  150. S. Sugahara, and M. Tanaka, “Atomic-Scale Surface Morphology of Epitaxial Ferromagnetic MnAs Films Grown on Vicinal GaAs(111)B Substrates”, The 8th Joint MMM-Intermag Conference, San Antonio, TX, USA, January 7-11, 2001, paper AE-05, p. 30.
  151. M. Matsumura, K. Ikeda, J. Yanase, and S.Sugahara, “Atomic-Layer-Epitaxy of Silicon”, The 10th Seoul International Symposium on the Physics of Semiconductors and Applications, Cheju, Korea, November 1-3, 2000, paper B8, p. 67.
  152. T. Fukumura, S. Sugahara, and M. Matsumura, “Deposition and Characterization of Perfluoro-Methyl Silica Films”, The 197th Meeting of the Electrochemical Society, Toronto, Canada, May 14-18, 2000, paper 219.
  153. S. Sugahara, T. Kadoya, K. Usami, T. Hattori, and M. Matsumura, “Preparation and Characterization of Low-k Silica Film Incorporated with Methylene Groups”, The 6th International Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC2000), Santa Clara, CA, USA, 2000, p. 27.
  154. S. Sugahara, T. Fukumura, and M. Matsumura, “Chemical Vapor Deposition of CF3-Incorporated Silica Films for Interlayer Dielectric Application”, The 196th Meeting of the Electrochemical Society, Honolulu, HI, USA, October 17-22, 1999, paper 746.
  155. S. Sugahara, and M. Matsumura, “Oxidation Mechanism of Fluorocarbon-Incorporated Silica for Interlayer Dielectric Materials”, E-MRS 1999 Spring Meeting, Strasbourg, France, June 1-4, 1999, paper L-III.2, p. L-4.
  156. S. Sugahara, M. Matsuyama, K. Hosaka, K. Ikeda, Y. Uchida, and M.Matsumura, “A novel hetero-epitaxy technique for germanium on silicon (100) surface based on atomic-layer-epitaxy”, MRS 1998 Spring Meeting, San Francisco, CA, USA, April 13-17, 1998, paper FF9.4, p. 489.
  157. S. Sugahara, K. Hosaka, and M. Matsumura, “Hydrogen-Induced Abstraction Mechanism of Surface Methyl Groups in Atomic-Layer-Epitaxy of Germanium”, The 4th International Symposium on Atomically Controlled Surfaces and Interfaces (ACSI-4), Tokyo, Japan, October 27-30, 1997, paper PC13, pp. 248-249.
  158. K. Ikeda, S. Sugahara, Y. Uchida, T. Nagai, and M. Matsumura, “Formation of Atomically Abrupt Si/Ge Hetero-Interface”, The 1997 International Conference on Solid State Devices and Materials (SSDM1997), Hamamatsu, Japan, September 16-19, 1997, paper D-11-4, pp. 532-533.
  159. S. Sugahara, and M. Matsumura, “Modeling of Germanium Atomic-Layer-Epitaxy”, The 4th International Symposium on Atomic Layer Epitaxy and Related Surface Processes (ALE-4), Linz, Austria, July 29-31, 1996, paper Mo14:45.
  160. S. Morishita, S. Sugahara, and M.Matsumura, “Atomic-Layer Chemical-Vapor-Deposition of Silicon-Nitride”, The 4th International Symposium on Atomic Layer Epitaxy and Related Surface Processes (ALE-4), Linz, Austria, July 29-31, 1996, paper PSi/Ge2.
  161. T. Kitamura, S. Sugahara, S. Imai, and M. Matsumura, “A Proposed Atomic-Layer-Deposition of Germanium on Si(100)”, The 1996 International Conference on Solid State Devices and Materials (SSDM1996), Yokohama, Japan, 1996, paper B-2-4, pp. 58-60.
  162. S. Sugahara, T. Kitamura, S. Imai, Y. Uchida, and M. Matsumura, “Ideal Monolayer Adsorption of Germanium on Si(100) Surface”, The 3rd International Symposium on Atomically Controlled Surfaces and Interfaces (ACSI-3), Raleigh, NC, USA, October 12-14, 1995, paper 16.09, p. 87.
  163. S. Sugahara, E. Hasunuma, S. Imai, and M. Matsumura, “Modeling of Silicon Atomic-Layer-Epitaxy”, The 3rd International Symposium on Atomically Controlled Surfaces and Interfaces (ACSI-3), Raleigh, NC, USA, October 12-14, 1995, paper 16.11, p. 90.
  164. S. Sugahara, M. Kadoshima, T. Kitamura, S. Imai, and M. Matsumura, “Atomic Hydrogen-Assisted ALE of Germanium”, MRS 1994 Fall Meeting, Boston, MA, USA, November 28 - December 2, 1994, paper D.
  165. S. Sugahara, T. Kitamura, S. Imai, and M. Matsumura, “Atomic Layer Epitaxy of Germanium”, The 3rd International Symposium on Atomic Layer Epitaxy and Related Surface Processes (ALE-3), Sendai, Japan, May 25-27, 1994, paper P26, p. 110.
  166. S. Sugahara, O. Sugiura, and M. Matsumura, “Electronic Structures of Si-Based Manmade Crystals”, The 1992 International Conference on Solid State Devices and Materials (SSDM1992), Tsukuba, Japan, 1992, paper A-6-4, pp. 560-562.
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